IEC 61000 -4 -2 is the most commonly used international industry standard for evaluating and qualifying product designs for ESD immunity. We perform these product design evaluations for a variety of reasons such as trouble shooting product malfunctions, developing stronger designed-in ESD immunity, diagnostics of “no trouble found” field failures, resolution of temporary upsets, and evaluation of prototypes.
Often customized stress testing is necessary to evaluate applications not adequately covered by IEC 61000-4-2. This is because there are countless scenarios that are not replicated by standardized testing. We specialize in developing these application appropriate test plans and have successfully resolved complex design issues.
While IEC61000-4-5 surge testing is primarily intended for qualifying system robustness against extremely energetic pulses from lightning, at lower levels, the long pulses (microseconds instead of nanoseconds) can provide important information on system and device robustness beyond the ESD regime and into targeted or simulated EOS events. While most IEC61000–4–5 testers are intended for kilovolt and kiloamp levels, dropping resistors are often added which change the waveshape and repeatability of the testing. We utilize low-voltage testing in order to characterize devices accurately at only a few to less than a hundred Volts and Amps giving consistent real-time failure characterization of simulated EOS events.
Current Reconstruction Scanning and Analysis (for Hard Failures and Damage)
With current reconstruction, a system need not be running, nor even operational. In this mode, the scanning probe is used much as it is with EMI scanning, except that an ESD–like current pulse is injected into nodes of interest to identify the path and intensity of the injected energy as it is directed and dissipated throughout the system. Current Reconstruction operates effectively on the reverse principle of the ESD susceptibility scanning technique.
At each point on the grid, a sample is measured from the repeated pulse from which the current through local traces can be inferred. This creates a moving map of discharge currents enabling the designer to “see” into a zap event as it affects the system.
ESD Susceptibility Scanning and Analysis (for Soft Failures)
With EMI scanners, a running system's emissions are monitored with a spectrum analyzer and a near field probe and plotted on a 3D visualization grid. This helps compliance engineers analyze and debug shielding and RF emissions problems. ESD susceptibility scanning techniques build on these well known EMI scanning methodologies.
Rather than acting as a receiver, the scanning probe is driven by a special TLP pulser at each step over a running system or PCB. The intensity of the pulse is increased until a sufficient local noise pulse coupled into the system upsets the normal operation of the device, similar to the failure criteria defined for system level ESD testing (i.e. system resets, data loss, lockup, etc.)
Plotting these values creates a “susceptibility map” which indicate areas of relative potential ESD susceptibility, or “hotspots.”
Hybrid Scanning and Analysis (Interrelated Hard and Soft Failures)
Comparing Current Reconstruction scans with different components or different layout configurations can give quantitative design validation and margin enhancement characterization. Comparing Current Reconstruction maps to Susceptibility Scanning maps can provide early warnings of trouble where known ESD entry vectors channel energy into or near susceptible ESD “hotspots.” This hybridization of techniques can be included in Product Design Reviews, or to create custom Design Guidelines for Design Process Reviews.
Product Design Review
We evaluate existing designed-in ESD protection strategies for ICs, Circuit Boards, Flat Panels and Systems to identify either enhancement opportunities or to help resolve design issues. This is customized work done in collaboration with clients and industry experts as needed, and utilizing an array of scanning and analysis tools available to Dangelmayer clients.
Design Process Reviews
Successful designed-in ESD protection requires timely planning, gathering of pertinent data and application appropriate testing. When done correctly from day one, completed products are virtually immune to either ESD damage or ESD upsets due to ESD transients. Additionally, the incremental cost of the end product is often minimal. Whereas, retrofitting existing designs can be very costly or impossible to completely resolve. We conduct thorough ESD reviews of the procedures for product development based on years of experience in R & D communities such as Bell Laboratories. We provide recommendations to optimize the development process and ESD designed-in protection.
Failure Analysis Support
Failure Analysis Report Analysis
We provide expert analysis of FA reports and determination of the cause of failure. Differentiation among CDM, HBM, CBE and EOS failure modes is often possible.
We develop customized stress tests to replicate IC failure signatures
Failure Root Cause Analysis
Customized application of the above techniques is use to isolate the root cause of product failures. Our team achieves this as a result of years of experience, advanced expertise and collaboration with subject matter experts.