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Success Stories » ESD Myths and Latency

3 ESD Class 0 Success Stories | ESD Myths, Latency & Success Stories | EOS Misdiagnosis & Success Story | Economic Benefits | Testimonials

ESD Myths, Latency and Success Stories

There are a number of common misunderstandings and controversies about electrostatic discharge (ESD) program management that can have significant impact on the implementation and maintenance of the ESD program.  These misunderstandings or “myths” result in unnecessary expenditures and/or result in a compromise of the program integrity.  These myths and controversies, such as latency are often cited by skeptics not wanting to adhere to certain standard ESD procedures.  As a consequence, it is important to identify and dispel the myths as well as to understand the potential impact of latent failures.

This discussion outlines five of 15 common myths and three supporting success studies as well as a success study on latency.  The balance of the myths and several additional success studies are discussed in ESD PROGRAM MANAGEMENT [1].  The myths and success studies presented here were chosen to provide real-world examples of how an ESD program can be strengthened by understanding the fallacy in each of the myths.  This understanding will result in more reliable products that are also more cost competitive.

Although not a myth, latency it is a significant reliability consideration that is surrounded with controversy. Some experts will argue that latency is virtually non-existent and others will claim that it is the dominant failure mode.  Reality lies somewhere in between. The Latency study below cites irrefutable evidence of latent failures in alarming proportions that must be factored into ESD programs and product design.

Common Myths

Myth2:PWB Assemblies Are Not ESD Sensitive

Many individuals believe that once a component is inserted into a printed wiring board (PWB) assembly, the component is no longer ESD sensitive.

Truth:  The ESD failure rate and sensitivity of a component can increase after it is inserted into a PWB assembly. One reason for this occurrence is that sensitive device junctions may become more easily accessed through the conductor paths of the PWB assemblies.  Furthermore, laboratory tests have quantified this phenomenon.

In one such test, the withstand voltage of a sensitive bipolar component was determined to have increased by only 20 percent (that is, virtually no increase) when the component was tested in a PWB assembly. Even a metal shunt on the edge connector of this assembly had little impact on the sensitivity of the component. Thus, the component was equally sensitive on or off of the PWB assembly.

At the very least, ESD controls are as important for PWB assemblies as they are for components. For instance, Success Studies one and two below cite instances where significant device failure rates developed at the circuit board level.

Myth 3: One ESD Sensitivity Classification Is Sufficient for All Areas

Many companies view multiple work area classifications as unnecessary and cumbersome.  These companies arbitrarily assign the same classification to all ESD sensitive components or assemblies.  As a consequence, they lose the opportunity to maximize the flexibility and cost effectiveness of the program.

Truth:  Component sensitivities vary widely and Class 0 controls are too cumbersome for general application.  For example, the differences between Class 0 and Class I components can be significant and standard ESD procedures are often insufficient for Class 0 devices. Therefore, companies manufacturing a diverse range of products will need at least two classifications (Class 0 and Class I).

The secret to implementing a successful program is to use multiple classifications in such a manner that training is virtually the same for all employees. Engineering provides the appropriate ESD control tools based on sensitivity and employees are trained to use all tools with the same techniques.

In summary, companies must adopt a minimum of two area classifications.

Myth 4: Human Body Model (HBM) Data Are Sufficient for Detecting Device Sensitivity Levels

Truth: Companies that rely solely on HBM data fail to recognize the importance of charged device model (CDM) Data. Because the HBM was the first model developed, the most readily available data is HBM and the vast majority of programs are based on HBM thresholds. As a result, HBM counter measures have become highly effective. CDM failures, however, are now far more prevalent in factories because it is almost impossible to prevent components and assemblies from becoming charged. This is especially true due to the prevalence of high-throughput automated assembly and test equipment used in most factories. Thus, CDM [3] data are vital to any ESD program.

For example, at the Lucent Technologies facility in North Andover, Massachusetts, no HBM failures have been reported over the past 15 years. On the other hand, CDM failures continue to occur on occasion. It should also be noted that some companies do not fully understand the relevance of the machine model (MM). The MM is a variation of the HBM and does not provide a reliable simulation of ESD damage caused by machines. MM typically produces the same failures as HBM but at approximately one-tenth the HBM threshold. As a result, the MM data produce little additional information of use in implementing ESD controls and often prompts companies to overreact. However, the MM is a useful tool for Failure Mode Analysis (FMA).

In summary, a sound ESD program must be developed and maintained on the basis of both the HBM and CDM. The MM can be useful as a diagnostic tool.

Myth 8: Grounded Metal Is a Safe Surface for ESD Sensitive Components or Assemblies

Truth: Conductive materials are not safe surfaces for components that may be charged. This is true regardless of whether or not the conductive material is grounded.  The CDM event occurs rapidly between two objects and the resistance to ground (including a 1-megohm resistor) has virtually no impact.

Myth 9: Designed-in ESD Protection Precludes the Need for ESD Handling Controls

Truth: Although designed-in protection generally improves the withstand voltage of components and PWB assemblies, this protection has technological limits. Total immunity is nearly impossible to achieve without an enclosure.  Tradeoffs between performance and designed-in protection are very common.  As a result, a sound ESD program requires a combination of good design and sound manufacturing practices.

Success Stories

Success Story 1: ESD (Field-induced CDM) Caused by Charged Plastic Faceplate

This success study illustrates the fallacy explained in four of the myths.  The high failure rates cited below occurred to circuit boards (Myth #2), the failures were CDM and not HBM (Myth #4), grounded metal test probes triggered the damaging CDM transients (Myth #8), and the designed-in device protection (1,500 volts) exceeded design requirements but was insufficient to prevent damage from occurring (Myth #9).

A recent experience in one factory pointed out that the root cause of ESD problems can be a very simple, seemingly harmless part. Many printed wiring assemblies (circuit packs) include a cover or "faceplate" which provides a protective covering when the pack is installed in a shelf (Figure 1). In many designs, these faceplates are metallic and grounded to provide good electromagnetic compatibility (EMC). However, to keep material costs down, they are often made of insulating plastic. EMC design issues are then addressed using other techniques.

In the success at hand, a system was designed using plastic faceplates and was in low-level production for more than a year without any indication of a significant problem. At one point, however, the removal rate of a certain linear CMOS part began to rise. The rate averaged 2.5 percent with rates as high as 40 percent on certain days.  The device failures were observed after circuit pack test and the observed electrical signature was excessive leakage current between two pins on the device. The leakage was high enough to cause the circuit pack to fail its functional requirements.

Figure 1: Circuit Pack with Plastic faceplate and Schematic
Figure 1: Circuit Pack with Plastic faceplate and Schematic

These observations and subsequent FMA pointed strongly to ESD as the source of the problem. The production line had a well-designed ESD program known to be in compliance with the Lucent program. Furthermore, a careful analysis of the line produced no indication of why this particular part was failing at higher than normal levels.

Other possible changes were also investigated. For example, the supplier of the integrated circuit was consulted to determine whether any changes had been made to the design which might affect its ESD withstand voltages. No such changes had been made. In fact, the device had been tested for its vulnerability to ESD as is required for use in Lucent equipment and met all requirements. Most significantly, its charged-device model (CDM) withstand voltage was 1,500 volts which is well above requirements.

While investigating changes in the design or materials, it was learned that the source of the plastic for the faceplate had changed around the time that the failure levels began to increase. Both the base resin and the molder had changed, it was then found that the electrostatic voltages on the faceplates were extremely high, with 10 kV being typical, and that these voltages persisted for days or weeks. Laboratory investigations then showed that the faceplates from the new source tended to charge to levels about five times higher than the previous ones and that the charge retention was much longer.

For reasons that will become clear in this discussion, the board/ device level failure mode analysis was difficult. Eventually, it was demonstrated that the exact failure as was observed in the factory could be produced by tribocharging the faceplate and then touching (grounding) the circuit pack in a particular way. This was a classic example of a field-induced charged-device model failure. Initial investigations into the failure mechanism of the circuit packs indicate that the pin (21 or 22) which failed in the factory (Figure 1) was never physically touched during testing and/or handling of the circuit pack.  This was surprising because the CDM failure of a pin requires that the pin be grounded. Thus, further studies were conducted in the laboratory which confirmed that the pin 21-22 leakage current could be produced by touching a pin on a transformer mounted near the faceplate.

This pin was connected by a low resistance bus on the PWB to pin 36 of the CMOS device (Figure 1).  Thus, the pin which exhibited the failure was different than the pin stressed. This is not unusual for CDM events. However, this is seldom observed in routine qualification of devices because after-stress testing of the device is usually only done after all pins have been stressed. Therefore, it is important in FMA investigations to stress the device in a manner which resembles as closely as possible the actual sequence of events in order to confirm the failure mechanism.

The next step was to understand how the charging and discharging events were occurring in the factory.  Subsequent investigations showed that the faceplates charged very easily during shipping and handling and were very difficult to neutralize reliably.  While several scenarios for improved shipping and handling procedures were investigated, ultimately a materials solution emerged as the most attractive alternative.  The discharges were found to be occurring during the testing of the circuit pack. The entire scenario is represented schematically in Figure 5-3. When the circuit pack with its charged faceplate was placed in the "bed-of-nails" tester, the first test probe to touch the pack touched a pin on the transformer near the charged faceplate. The transformer pin was about 1/2-inch from the charged faceplate.   Because the voltages on the

Faceplates were very high, it is easy to imagine that the effective induced voltage as seen by the transformer and device exceeded the 1,500-volt withstand voltage.

In conclusion, the cost of repair and replacement for this failure was estimated to be $500 thousand to $1 million, not including the costs of the FMA investigations.  However, the economic impact could have been much worse if Lucent had not had a long-standing requirement for minimum CDM performance. For example, if the CDM withstand voltage had been a 150 volts, and then faceplate voltages of as little as 1 kV could have produced comparable failure levels. This is significant because the solution to this

problem — finding a lower charging material — would not have been effective.  Furthermore, with the high charging material, the dropout rate could have been in the 50 percent range with a cost impact of $10-20 million and the viability of the product line would have been threatened.

Success Study 2: Ultrasensitive Device Failures on Circuit Boards

The high failure rates cited below occurred to circuit boards (Myth #2) and special procedures had to be developed to successfully handle an ultrasensitive (Class 0) device (Myth #3).

The trend toward including ultrasensitive devices in the manufacturing process calls for a separate discussion of the problems and difficulties that can arise in handling these devices. One such success was revealed with the introduction of an N-type metal oxide semiconductor (NMOS) device that had an ESD withstand voltage of 20 volts. Major problems were encountered during device fabrication as well as during the manufacture of printed wiring board (PWB) assemblies.

This low threshold was the result of the lack of any protection circuitry on the high-speed pins of the device. The designers presumed that any such circuitry would prevent the device from performing its intended function.

Circuit Board (PWB) Assembly

Figure 2: Circuit Pack Yield Variation
Figure 2: Circuit Pack Yield Variation

Extreme fluctuations in PWB assembly yields (Figure 2) were occurring during the start of "ramp up", that period during which production quantity begins to increase rapidly in order to meet the ultimate levels of production. Between the months of

June and September, the removal rate varied dramatically between 10 and 30 percent.   In actual lot-to-lot observation, some lots showed a 100-percent drop out in which every single device was defective.

Due to the scarcity of these 20-volt NM03 devices, the cost implications of their continued failure were very high. Therefore, a detailed investigation was undertaken. Through failure analysis, it was determined that the devices were failing due to ESD.  In fact, it was demonstrated through failure mode analysis at Bell Laboratories that virtually all of the failures were ESD-induced. However, no solution for handling a device that failed at 20 volts was readily apparent.

A special detailed audit was conducted and a number of people experienced in different aspects of the issue were consulted. A detailed inspection of the manufacturing line began and a plan of corrective action  was compiled. Based on that action plan, a task force was assembled and assigned to correct deficiencies in the line and to report weekly on what corrective measures had been taken. Because of the extreme seriousness of this situation, the weekly reports were channeled to high-level executives in the company.

Initially, many extraordinary handling precautions were instituted.  Even with all of this special attention and compliance with the procedures defined by Class I sensitivities, yields continued to fluctuate dramatically from June through September (Figure 2).

The solution to this particular problem was found in the introduction of a "top hat." A top hat is a conductive shunt that is placed on top of a device after it has been assembled to the PWB.  As soon as these problem-causing ultrasensitive devices were mounted on the PWB assembly, the shunt, that electrically shorted the leads together, was placed on top.  The board was then allowed to go through the production line in normal sequence. The results of the inauguration of that procedure during the month of September are clearly and dramatically recorded in Figure 2.  By mid-November the removal rate had dropped even further to around 2 percent. By the simple addition of a shunt to the devices, a dropout rate of 30 percent was reduced to 2 percent.

The simplicity of this solution is particularly striking in contrast to more common procedures involving every kind of ESD protective device known to science.  The use of so many kinds of precautions eventually becomes difficult to manage.  In successs such as this, when an ultrasensitive device is so easily damaged, the extraordinary measure of using a multitude of standard precautions may prove futile as well as expensive. The solution described here introduces a simple shunt into a Class 1 set of procedures. The incremental cost is trivial. A total expenditure of $1,000 provided the level of protection required.   Yet the dollar savings realized on the production line excluding overhead expenses, reached $6.2 million per year for this one device on this one line.  That is an impressive payback by any measure.

One additional benefit derived from this success was the impact that it had on the design community. Asked to justify a withstand voltage of 20 volts for the NMOS device involved in the project, designers responded by redesigning the device and raising the level of sensitivity to 1,000 volts HBM, a remarkable accomplishment. Some system level design changes were made to accommodate the new protection circuitry and maintain the system performance. 

In conclusion, this success study makes it clear that ultrasensitive devices can present a potential threat to production lines that may result in lost production and lost sales.  The financial implications are particularly unattractive when the cost of lost sales is added to the cost of lost materials.  In its final configuration, the PWB assembly is enclosed in a metal housing. Consequently, this ultrasensitive device has always been well protected in the field and has a low return level for ESD defects.

As a direct result of the experience outlined in this success study, minimum design requirements were modified and a new set of handling requirements (Class 0) were established and added to requirements.  It was apparent that a cookbook approach to establishing handling criteria for ultrasensitive devices would not work.For example, it is likely that some of the automated equipment used in the assembly process was causing the problem solved by the application of a top hat. Clearly, all of the wrist straps and ionization units in the world would not have solved this problem. Adding a shunt was not only necessary but sufficient to protect the device at great economic benefit. The solution offered tremendous economic leverage. In addition, a Class 1 shop was allowed, through this solution, to continue to do business as usual while protecting an ultrasensitive device.  Training considerations were minimized, and the impact on personnel significantly simplified.

Success Study 3: Latency

Although not a common myth, latency is a reliability issue.  This success history was selected to illustrate a latent failure due to prior ESD damage in a hybrid integrated circuit (HIC) design incorporating a bipolar silicon integrated circuit.

Figure 3: Latent ESD Failure
Figure 3: Latent ESD Failure

Irrefutable Evidence of Latency

The first evidence of a problem appeared in the early stages of initial production during a quality assurance sampling when three out of 15 PWB assemblies failed the system test. These PWB assemblies had just passed an identical system test as part of the manufacturing process, which did not include ESD protection.  Subsequent defect analysis revealed a bipolar junction on HIC "B" with excessive leakage in all three PWB assemblies. Also, the failing external HIC pin was routed directly to another HIC on the PWB and not to an external PWB assembly connector pin.

Later, an unrelated laboratory evaluation of 24 of the same type of PWB assemblies was initiated. The PWB assemblies were put into an operating system, tested successfully, and then left functioning in a secured area. During the next five days, five of the 24 PWB assemblies failed with the leakage condition described above.   Figure 3 is a scanning electronic microscope (SEM) photograph (at 4.800X) of the junction damage exhibited by all five failures.

Although it is difficult to see, there is a faint trace between the two conductors, indicated by the arrow.  The damage was subsequently duplicated by exposure to ESD. The threshold of damage was established at 450 volts human body model (HBM) for HIC "B" and at 1,000 volts HBM for the completed PWB assembly.

The circumstances surrounding these five failures were such that no one could have touched them once they were operating in the system. Additionally, the testing was done by remote access. Therefore, it is likely that these failures were latent due to prior ESD damage.

At approximately the same time, one customer reported that 17 PWB assemblies out of 31 failed 2 weeks after being successfully put into service.  All exhibited the same leakage condition as the five laboratory failures and were suspected of having latent ESD failures.

In comparing this failure activity to the in-house data above, a statistically significant difference is noted with a confidence level of 99 percent.  Likewise, a review of the field data indicated that this situation was extremely abnormal.  Therefore, unique and severe conditions triggered the 17 failures.  Further evaluation revealed that these PWB assemblies had been expedited through unusual channels in the dry winter months and that they had been transported in expanded polystyrene (EPS) trays.

Furthermore, these PWB assemblies were child boards and required assembly to the parent board on customer premises.  During assembly, it is particularly convenient and almost necessary for this installer to directly contact the conductor on the PWB leading to the indicated HIC pin, thereby increasing the probability of ESD damage.  Therefore, most likely the EPS packaging, in conjunction with the circumstances in the field, was probably a major factor leading to latent failure.  However, prior damage in the factory or in transit could not be ruled out.

Compared to the number of failures during early production, these failures were insignificant and were the only ones reported.  However, on the premise that it was an early warning, response was prompt—ESD precautions were incorporated throughout the manufacturing and shipping process and a Zener diode was added to the PWB assembly to shunt ESD transients to ground.  Adding the diode improved the PWB assembly threshold from 1,000 volts to something in excess of 15,000 volts. As a longer-term solution, HIC "B" was redesigned to incorporate additional protection.

In conclusion, latent failure due to prior ESD damage was witnessed under laboratory conditions and was suspected of having occurred on customer premises while the PWB assemblies were in service as a result of EPS packaging. This, in conjunction with other reports of latency[2], supports previous conclusions that ESD damage can adversely affect the reliability of bipolar devices.

Side bar – list the 15 common myths

  • Myth 1: "Small" Companies Cannot Afford Large Company ESD Programs
  • Myth 2: PWB Assemblies Are Not ESD Sensitive
  • Myth 3: One ESD Sensitivity Classification Is Sufficient for All Areas
  • Myth 4: Human Body Model (HBM) Data Are Sufficient for Detecting Device Sensitivity Levels
  • Myth 5: Air Flow Causes Charging
  • Myth 6: Metalized or Highly Conductive Shielding Layers Are Essential
  • Myth 7: Highly Conductive Materials Provide Increased Protection
  • Myth 8: Grounded Metal Is a Safe Surface for ESD Sensitive Components or Assemblies
  • Myth 9: Designed-in ESD Protection Precludes the Need ESD Handling Controls
  • Myth 10: Smocks Are an Essential Element of an ESD Program
  • Myth 11: The "Three-Foot Rule" Is an Important ESD Safeguard
  • Myth 12: Touch Ground Procedures Are Effective
  • Myth 13: One Heel Grounder Is Sufficient Protection
  • Myth 14: Individuals Wearing Wrist Straps at ESD Work Stations Cannot Damage Sensitive Devices or Assemblies
  • Myth 15: Supplier Data Sheets on ESD Materials Can Be Accepted Without Question


  1. ESD PROGRAM MANAGEMENT, Second Edition, Ted Dangelmayer, Kluwer Academic Publishers, Second Printing 2001, Book ISBN 0-412-13671-6
  2. McAteer, O.J., and R.E. Twist, “Latent ESD Failures”, EOS/ESD Symposium Proceedings, EOS_4, 1982, p.41
  3. (1995) Duvvury and Amerasekera (TI) show the results of improving CDM protection in ICs using 0.35 micron LDD CMOS technology.