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Importance of CDM, CBE & Class 0

Class 0 Definition | Class 0 Case Study | EOS Misdiagnosis

Human-Body Model (HBM) has been the main thrust of ESD control and protection for the last two decades. During that time HBM ESD failures have become rare. Parallel to this, ESD failures related to device charging and production equipment have increased. In fact many companies now report that CDM is the cause of >99% of ESD failures. Dangelmayer Associates is uniquely positioned to resolve CDM, CBE and Class 0 issues since our team has done much of the pioneering in these areas dating back to the early 1980’s1. Our experience and expertise include but are not limited to CDM, CBE, EOS, Auditing, Training, S20.20 Pre-assessments, S20.20 Programs, ESD Quality Tracking Metrics, and Class 0 Certification.

Charged-Device Model (CDM):

The model which best represents device charging and production equipment is the Charged-Device Model (CDM). This model is a very different stress than the HBM and thus requires different device tests and different factory controls. The development of CDM tests has been slow because of the relatively high-speed nature of the CDM-current pulse compared to the HBM. The implementation of CDM controls has been slow because of the variety of ways the CDM stress can be realized in actual production. Because of this only a few companies initially pursued CDM controls and requirements and it is only in the last few years that the issue has become so severe that the IC industry has produced a series of “white papers”2 describing the emerging relative importance of CDM and HBM. The following excerpt is from White Paper II: “CDM has become the primary real world ESD event metric describing ESD charging and rapid discharge events in automated handling, manufacturing and assembly of IC devices. Its importance has dramatically increased in the last few years as package feature sizes, capacitance and pin count have scaled upward”. The following roadmap from this paper summarizes the situation.


1 R. Renninger, M-C. Jon, D.L. Lin, T. Diep and T.L. Welsher, “A Field-Induced Charged-Device Model

Simulator”, EOS/ESD Symp. pp. 59-71, 1989.

2Industry Council on ESD Target Levels.  A) White Paper 1:   A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements,” August 2007, at www.esda.org;  B) “White Paper 2: A Case for Lowering Component Level CDM ESD Specifications and Requirements,” Revision 2, April 2010, at www.esda.org.


roadmap of CDM ESD thresholds

Figure A-1 – Roadmap for CDM ESD Thresholds with Emerging Technologies


Charged-Board Events (CBE)

Most IC failure analysis data, which is based on knowledge of failure signatures seen in standard HBM and CDM tests, has caused many to conclude that ESD failures are relatively rare when compared to other electrical failures commonly classified as electrical overstress (EOS).  Recent data and experience reported by several companies and laboratories now suggest that many failures previously classified as EOS may instead be the result of ESD failures due to Charged Board Events (CBE)3 .   A charged board stores much more energy than a device (IC) because its capacitance is many times larger.  In fact, the charge (energy) transferred in the event is so large that it can cause EOS-like failures to the components on the board.   The failure in Figure 2 was identified by many FA experts as EOS even though it was actually a CBE-induced failure.   Unfortunately, many failures are misdiagnosed as EOS because FA engineers are not aware of CBE.  This distorts the common Pareto chart for IC defects (Figure 3).  The actual occurrence of ESD is therefore likely to be significantly higher than is often reported4 and, thus, is often the greatest cause of device failures today.  


figure 2   figure 3

Figure 2                                                          Figure 3


Class 0

Class 0 is a short-hand term for devices which may require special handling considerations.  While there is no complete industry standard for the term, it is usually described in terms of the device sensitivities.   A common definition is:   any device with an HBM or CDM threshold less than 250 volts.   Since CDM accounts for >99% of ESD failures today it also represents >99% of Class 0 failures.



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3 A. Olney, B. Gifford, J. Guravage, A. Righter, “Real-World Printed Circuit Board Failures,”  EOS/ESD Symposium Proceedings, EOS-25, pp. 34-43, 2003.


4 EOS versus ESD Misdiagnosis: Charged-Board Events Are a Growing Industry Concern  G. T. Dangelmayer, T. L. Welsher, and A. Olney, Medical Electronics Manufacturing, Spring 2009